The human voice may be represented as an analog signal, but digital transmission of any signal over great distance is preferred for several reasons. For example, low signal-to-noise ratios as seen by detectors caused by variations in distance between transceivers may be compensated for by introducing error correction and error detection in digital sequences. Further, multiplexing, switching and repeating hardware is more economical and easier to design in a digital transmission system. Consequently, in cordless and wireless applications between handset units and base units, speech encoding and decoding is used to convert a human analog voice signal to a digital format for transmission over the wireless interface.
The input to the speech encoder is usually in the form of a continuously variable voltage where that voltage changes value over time to represent the instantaneous sound pressure level at the microphone device. Within the speech encoder the digital signal generated by the encoder is used to construct an approximation of the applied speech signal within the encoder and the digital signal is generated in a manner to minimize the difference between the applied speech signal and the encoder's approximation of that signal.
The continuously variable slope delta modulator (CVSD) is a simple alternative to more complex conventional conversion techniques, such as adaptive differential pulse code modulation (ADPCM) encoding and decoding techniques, in systems requiring digital communication of analog signals. The CVSD analog to digital converter (A/D) is well suited to the requirements of digital communications and is an economically efficient means of digitizing analog inputs for transmission, and is described below to illustrate how encoding parameters may be generated. CVSD circuits are commercially available, for example, as an MC3418 CVSD Modulator/Demodulator integrated circuit from Motorola, Inc.
A block diagram of a CVSD encoder of the prior art is shown in FIG. 1A. The innermost control loop of a CVSD converter is a simple delta modulator including a comparator 101, sampler 103, slope polarity switch 104 and integrator 102. The delta modulator consists of the comparator 101 in the forward path and the integrator 102 in the feedback path of a simple control loop. The comparator 101 receives the input analog signal and the output signal of the integrator 102. The output signal e(t) of the comparator 101 may be sampled in the sampler 103, and the sample values reflects the sign bit value of the difference between the input voltage signal and the integrator output signal. The sign bit value is a digital signal applied to a slope polarity switch 104 which controls the direction of ramp in the integrator 102. A clock signal is usually applied to the comparator 102 so as to produce a synchronous and band-limited serial bit stream DIGITAL OUT.
The advantages of the delta modulator are simplicity and serial format of its output. The delta modulator limitations are its ability to accurately convert the input signal to within a limited digital bit rate. The analog input signal should be band limited and amplitude limited. The frequency limitations are governed by the nyquist rate, while the amplitude capabilities are set by the gain of the integrator. The frequency limits are bounded on the upper end; that is, for any input bandwidth there exists a clock frequency larger than that bandwidth which will transmit the signal with a specific noise level. However, the amplitude limits are bounded on both upper and lower ends. For a particular signal level, one specific gain will achieve an optimum noise level. Unfortunately, the basic delta modulator has a small dynamic range over which the noise level is constant.
Consequently, the CVSD encoder also includes circuitry, including a level detect processor 105 and slope magnitude control 106, which increases dynamic range of the delta modulator for a given clock frequency and input bandwidth by adjusting the gain of the integrator 102. The level detect processor 105 implements a level detect algorithm which monitors the past few outputs of the delta modulator in a simple shift register. The register may be 4-bits long. One CVSD algorithm simply monitors the contents of the shift register and indicates if it contains all 1s or 0s, which condition is defined as "coincidence." When coincidence occurs, the gain of the integrator 102 may be too small. The coincidence output value charges a single-pole low pass filter of the slope magnitude controller 106. The voltage output of this filter controls the integrator gain from slope polarity switch 104 through a pulse amplitude modulator whose other input is the sign bit or up/down control.
Also, the simplicity of the all 1s, all 0s algorithm provides a measure of the average power or level of the input signal. Other techniques provide more instantaneous information about the shape of the analog input signal curve. The purpose of this one algorithm is to control the gain of the integrator 102 and to increase the dynamic range. The effect of this algorithm is to compand the input signal.
A block diagram of a CVSD decoder of the prior art is shown in FIG. 1B. The delta modulator of the CVSD decoder of FIG. 1B includes a sampler 113, a slope polarity switch 114, and integrator 112. The clocked serial bit stream DIGITAL OUT is transmitted to and received by the CVSD decoder as DIGITAL IN, which may include added noise and bit errors. This serial bit stream is applied to the integrator 112 of the delta modulator through slope polarity switch 114 in a similar manner to that of the encoder integrator 102 and slope polarity switch 104. To the extent that the integrator 102 at the transmitting locations tracks the input signal, the remote receiver reproduces the input signal.
However, if a CVSD encoder employing the level detect algorithm previously described is played into a delta modulator of a CVSD decoder, the output signal of the delta modulator will reflect the shape of the input signal, but the level values of output signal will be equal. Thus a similar level detect algorithm is provided in the CVSD decoder by the level detect processor 115 and slope magnitude controller 116 to restore level variations because the digital bit stream in the channel appears as if it were from a standard delta modulator with a constant level input signal. The level detect algorithm is repeated in the receiver and thus the level data is recovered in the receiver. Because this algorithm operates only on the past serial data, it changes the nature of the bit stream without changing the channel bit rate. Low pass filtering of the AUDIO OUT signal eliminates most of the quantizing noise, if the clock rate of the bit stream is an octave or more above the bandwidth of the input signal. Depending on a desired perceived voice quality, voice bandwidth typically is 4.0 kHz and the clock signal rates are typically from 8.0 kHz.
As stated previously, for CVSD encoding the approximation signal is generated by simply integrating the digital data, thus a digital one means "ramp the approximation signal up one `unit` of voltage from the present value" and a digital zero means "ramp the approximation signal down one `unit` of voltage from the present value", where `unit` might be a variable containing an integer value from 1 to 16. The digital value generated (one or zero) is the value that will cause the difference between the applied speech signal and the encoder's approximation signal to be minimized.
Additionally, for CVSD, the generated bits may be passed through a four or three bit shift register so that several contiguous bits can be analyzed as a group. At the conclusion of each bit transmission time the contents of the shift register are analyzed. If all bits within the register are "one" or "zero" the value of `unit` might be doubled (but not allowing `unit` to be larger than 16), and if all bits in the shift register are not the same value the value of `unit` might be halved (but not allowing `unit` to be less than 1). Thus, if several bits of the same value are generated, the approximation signal is lagging behind the source signal, and the step size of the up/down ramp will be increased. On the other hand, if the bits in the register were never all the same value the step size would be reduced.
The parameters used by the encoder and decoder approximation generators are identical in this case (but it may not always be beneficial for them to be identical). The key parameters are to ramp linearly during one bit time (by means of the integrator), to double the step size if the last N generated bits were the same value or halve the step size if the last N generated bits were not the same value, the specific value of N, etc.
As is apparent from the discussion of the CVSD encoder, any encoder may include a set of parameters to optimize the encoding process of an analog signal. For the CVSD case, these particular parameters might benefit users with higher pitched voices more than those users with lower pitch voices. A different set of parameters might produce better subjective listening scores when lower pitched voices were encoded/decoded compared with higher pitched voices. For an ADPCM based system, for example, as is known in the art, the ADPCM algorithm may try to select a quantization step size large enough to accommodate a maximum peak-to-peak range of an input signal, while also trying to select a quantization size small enough to minimize the variance of quantization noise. Subjective listening scores when lower pitched voices were encoded/decoded with ADPCM compared with higher pitched voices may show a dependence on this trade-off in quantization step size. Consequently, there is a need for a speech encoding system in which one set of parameters which may be more suitable for encoding a person's speech may be used rather than another set of parameters.
Further, in cordless, wireless or similar telecommunication applications with analog baseband processing a "soft signal fade" occurs when characteristics of the transmission media between a handset unit and a base unit changes, for example, when a handset moves through a residence. Soft signal fade is defined as slowly degrading signal/voice quality as heard in the handset. Since a user can hear or sense performance rolloff in the link (reduced link margin), the user may make adjustments to increase the link performance. However, in a digital transmission link, when the link margin is reduced, whole portions of speech blocks are lost since bit error tend to be "bursty" in nature.